H - Electricity – 04 – L
Patent
H - Electricity
04
L
H04L 7/027 (2006.01) H03K 5/007 (2006.01) H03K 5/08 (2006.01) H04N 5/08 (2006.01) H04N 7/035 (2006.01) H04N 5/445 (2006.01)
Patent
CA 2130822
A composite synchroniza- tion extraction circuit is particu- larly suited for receiving compo- site video signals containing closed captioning data in raster scan line (21) by means of a sig- nal CMOS integrated circuit de- vice. A dual mode voltage clamp is realized in CMOS technology. The clamp includes temperature compensated current sources in the form of complementary cur- rent mirrors through which a clamped composite synchroniza- tion node is charged and dis- charged with the aid of a compar- ator, the output of which controls a transistor for charging the com- posite synchronization node. De- tected pulse amplitude is set by slicing (24, 25) the incoming pulse at the back porch level and then doubling the amplitude with an amplifier and comparing that level with the back porch level as derived from a sample-and- hold device. Frequency and phase synchronization is accomplished by a combination of frequency lock Loop and phase lock loop (27, 28) working in concert to generate a control voltage for a voltage controlled oscillator in a. flywheel mode. The voltage con- trolled oscillator (27) is not subject to noise in the incoming signal and provides a clean source of timing information for the cir- cuit.
Berman Eric B.
Ganesan Apparajan
Jorden William B.h.
Mclaughlin Philip T.
Posner William H.
Eeg Enterprises Inc.
Extratek Inc.
Goudreau Gage Dubuc
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