Video tiling using multiple digital signal processors

Details Video tiling using multiple digital signal processors Video tiling using multiple digital signal processors

H - Electricity

04

N

H04N 5/262 (2006.01) G11B 27/031 (2006.01) H04N 7/18 (2006.01) H04N 5/44 (2006.01)

Patent

CA 2627060

A system and method for creating video tile arrays is disclosed. A first plurality of video streams produced by a first plurality of Analog to Digital Converters (ADCs) are received in a first Digital Signal Processor (DSP). The first DSP processes the first plurality of video streams to produce a partial video tile array stream. The partial video tile array stream is transferred to a second DSP. The second DSP receives a second plurality of video streams produced by a second plurality of video ADCs. The second DSP processes the partial video tile array stream and the second plurality of video streams to generate a tiled video stream. The tiled video stream comprises an array of a plurality of video tiles that each correspond to a one of the first and second plurality of video streams.

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