Virtual cache

Details Virtual cache Virtual cache

G - Physics

06

F

354/233

G06F 13/00 (2006.01) G06F 12/08 (2006.01)

Patent

CA 1139451

Case 04-4181-U.S. APPLICATION OF ROBERT H. DOUGLAS AND THOMAS L. PHINNEY VIRTUAL CACHE ABSTRACT A computer system includes a main memory and a cache memory arrangement, wherein a cache memory unit is associated with each of the several CPU's in the system. Each cache responds to the virtual address signals issued by the associated CPU, In parallel with a mapper unit which, in turn, converts the virtual address signals to physical address signals for addressing the main memory. The cache is subdivided into subunits each responding to a particular program of a multiprogram CPU. When any of the CPUs address a shared portion of the main memory, the mapper unit recognizes the address of the shared portion of the main memory and issues an inhibit signal to inhibit the operation of the cache memory unit to prevent data from the shared portion of the main memory from being stored in the cache.

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