Virtual memory address fetching

Details Virtual memory address fetching Virtual memory address fetching

G - Physics

06

F

354/239

G06F 12/10 (2006.01)

Patent

CA 1266530

Abstract of the Disclosure A hybrid hardware/software implementation of a translation look-aside buffer (TLB) is disclosed for improving the efficiency of address translation in a computing system utilizing a virtually addressed memory. Through the use of the present invention, complex hashing routines can be used to address entries in a virtual address translation table (VATT) within the system's physical memory, without increasing the complexity or significantly reducing the performance of the TLB fetch hardware.

515434

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