G - Physics – 06 – F
Patent
G - Physics
06
F
354/239
G06F 12/10 (2006.01) G06F 12/14 (2006.01)
Patent
CA 1200917
VIRTUAL MEMORY ADDRESS TRANSLATION MECHANISM WITH CONTROLLED DATA PERSISTENCE ABSTRACT Memory address translation and control system converts virtual memory addresses of a CPU into real memory addresses and for controlling memory functions. Address translation function comprises converting the virtual address into an effective address using a register set addressable by a small field of the CPU generated virtual address which converts the virtual address into an expanded form; and converting the effective address into a real memory address. The effective address is then used in the address translation step. To enhance the translation of frequently used virtual addresses, Translation Look-Aside Buffers (TLB) contain current effective to real address translations. The TLBs are addressed using a subset of the effective address. The contents of the addressed TLB is examined for a match with the effective address. When matched, successful address translation is possible and the real address stored in the TLB is available for system use. If not matched, the page frame tables stored in main memory are accessed for the desired effective address and if found the associated real address is accessed. Further a special data field is provided in both the TLBs and the page frame tables in main memory wherein a bit is provided for each line in the referenced page at a given effective to real address translation which bits may be used to indicate when a line of data has been accessed or altered.
443872
Chang Albert
Cocke John
Mergen Mark F.
Radin George
International Business Machines Corporation
Rosen Arnold
LandOfFree
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