Virtual time loop

H - Electricity – 04 – L

Patent

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Details

H04L 7/04 (2006.01) H04J 3/06 (2006.01) H04L 12/56 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 2245184

For facilitating the synchronization management in a system comprising a synchronized master (3) and a slave unit (1) communicating over a packed switched network, in particular an ATM network (5), the clock of a synchronized master unit (3) is recovered by the slave unit (1) e.g. by means of the adaptive mechanism. The slave unit (1) uses the recovered clock for transmission over the packet switched network (5). The depacketizing at the master side of the system is then performed using a clock signal provided directly from the synchronized network (3), i.e. without recovering the clock by means of the adaptive mechanism or the like.

Pour faciliter la gestion de la synchronisation dans un système comprenant un maître synchronisé (3) et un esclave (1) communiquant par l'intermédiaire d'un réseau de commutation par paquets, en particulier du type MTA (5), le signal d'horloge d'un maître synchronisé (3) est repris par l'esclave (1) par exemple au moyen d'un mécanisme adaptatif. L'esclave utilise ledit signal pour des transmissions sur le réseau de commutation par paquets (5). Le dépaquetage du côté maître du système s'effectue alors à l'aide d'un signal d'horloge directement fourni par le réseau synchronisé (3), c.-à-d. sans reprendre le signal d'horloge par des moyens adaptatifs ou similaires.

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