G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 12/08 (2006.01) G06F 12/10 (2006.01)
Patent
CA 2646473
An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.
La présente invention concerne un système de cache d'instruction ayant un cache d'instruction balisé virtuellement qui, d'une perspective logicielle, fonctionne comme s'il s'agissait d'un cache d'instruction balisé physiquement. Le système de cache d'instruction comprend également un moyen de traduction d'adresse qui agit en réponse à une instruction d'invalidation de traduction d'adresse et un circuit logique de contrôle. Le circuit logique de contrôle est configuré pour invalider une entrée dans le cache d'instruction balisé virtuellement en réponse à l'instruction d'invalidation de traduction d'adresse.
Sartorius Thomas Andrew
Smith Rodney Wayne
Streett Daren Eugene
Qualcomm Incorporated
Smart & Biggar
LandOfFree
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