Viterbi decoder comprising downsized circuits

Details Viterbi decoder comprising downsized circuits Viterbi decoder comprising downsized circuits

H - Electricity

03

M

H03M 7/00 (2006.01) H03M 13/41 (2006.01) H03M 13/12 (1995.01)

Patent

CA 2145228

A viterbi decoder for decoding a convolutional coded sequence transmitted from an encoder via a channel, wherein a plurality of paths representing a possible pre-coding data sequence and a path metric representing a likelihood of each path are calculated through a metric operation, and one of the plurality of paths is decided to be a decoding result through maximum likelihood decision based on the path metric, the viterbi decoder comprising: a metric converting unit for converting a value of the path metric to output a state metric, the value being converted into k when the value is more than k, where k is a predetermined integer within a range for the path metric, and left intact when the value is equal to or less than k; and a maximum likelihood deciding unit for deciding a minimum state metric using a path corresponding to the minimum state metric. The path metric is represented by m bits for each path, where m is an integer; and k is 2m-n-1, where n is an integer in a range from one to m-1 inclusive; the metric converting unit includes a plurality of metric converting circuits provided for the plurality of paths, respectively, each comprising m-n (n+1)-input OR gates that calculate OR's of upper n bits of a corresponding path metric and each lower bit to output (m-n)-bit state metric, whereby the maximum likelihood deciding unit decides the minimum state metric using the same.

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