Viterbi decoding method and circuit with accelerated...

Details Viterbi decoding method and circuit with accelerated... Viterbi decoding method and circuit with accelerated...

H - Electricity

04

Q

H04Q 7/20 (2006.01) G06F 11/10 (2006.01) H03M 13/41 (2006.01) H04L 27/06 (2006.01) H03M 13/12 (1995.01)

Patent

CA 2152238

In a first aspect of the invention, a Viterbi decoding circuit stores comparison result bits in a bit-accessible path memory unit. A back-trace is performed by setting a state value in a shift register, then shifting comparison result bits from the path memory unit into the shift register. A certain number of bits at the shift-in end of this register are supplied as read address bits to the path memory unit. In a second aspect of the invention, a Viterbi decoding circuit has selectors that first select old path metric values and branch metric values, which are added or subtracted to produce candidate path metric values, then select the candidate path metric values, which are subtracted to produce a comparison result bit representing the sign of their difference. These additions and subtractions are performed by the same arithmetic unit.

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