H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/133
H01L 21/308 (2006.01) H01L 21/283 (2006.01)
Patent
CA 1287188
VLSI DEVICES HAVING INTERCONNECT STRUCTURE FORMED ON LAYER OF SEED MATERIAL Abstract of the Disclosure In methods for making interconnect structures for semiconductor devices a layer of seed material is formed on a first substantially planar dielectric layer at predetermined locations where interconnect conductor is desired, a second substantially planar dielectric insulating layer is formed over the first substantially planar dielectric insulating layer, the second layer having openings extending therethrough at the predetermined locations to expose at least a portion of the seed material, and conductive material is selectively deposited on the exposed seed material to fill the openings. The seed material may be a material in the group consisting of aluminum alloys, refractory metals and metal silicides, or may be SiO2 selectively implanted with silicon ions. The insulating material may be SiO2. The conductive material used to fill the openings may be tungsten deposited by selective CVD or nickel deposited by selective electroless nickel plating. The steps of the methods may be repeated to form a multilevel interconnect structure. The methods are particularly suited to making interconnect structures for submicron devices.
587527
Junkin Charles William
Nortel Networks Limited
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