Vmos field aligned dynamic ram cell

Details Vmos field aligned dynamic ram cell Vmos field aligned dynamic ram cell

G - Physics

11

C

352/82.3

G11C 11/40 (2006.01) H01L 23/522 (2006.01) H01L 27/04 (2006.01) H01L 27/108 (2006.01)

Patent

CA 1133135

VMOS FIELD ALIGNED DYNAMIC RAM CELL Abstract of the Disclosure A semiconductor memory core structure comprised of an array of cells each having a single IGFET device formed in a recess located on one side of a diffused bit line and directly above a buried storage capacitor. The diffused bit line forms one source or drain region while the buried storage capacitor forms the other source and drain region. With the channel and gate between the two source and drain regions located on only one sidewall of the recess, the gate to drain and bit line capacitance is reduced, thereby providing increased signal power and a higher signal level to a sense amplifier than heretofore available.

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