G - Physics
06
F
G06F 17/10 (2006.01) G10L 19/14 (2006.01)
Patent
CA 2520421
A method and apparatus for implementing a vocoder in an application specific integrated circuit (ASIC) is disclosed. The apparatus contains a DSP core (4) that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further comprises a specifically designed slave processor to the DSP core (4) referred to as the minimization processor (6). The apparatus further comprises a specifically designed block normalization circuitry.
La présente invention concerne une technique et un appareil permettant de réaliser un vocodeur pour un circuit intégré à application spécifique (ASIC). L'appareil contient une mémoire centrale DSP (4) qui effectue les calculs en fonction d'une architecture RISC (à jeu d'instructions réduit). Le circuit comprend en outre un processeur spécialisé asservi à la mémoire centrale DSP (4), appelé processeur de minimalisation (6). Cet appareil comprend en outre une circuiterie spécialisée de normalisation de bloc.
Chang Chienchung
Kantak Prashant
Mcdonough John G.
Sakamaki Charles E.
Singh Randeep
Qualcomm Incorporated
Smart & Biggar
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