Voltage clamping circuit

Details Voltage clamping circuit Voltage clamping circuit

G - Physics

05

F

328/193, 323/4

G05F 1/44 (2006.01) G05F 3/24 (2006.01) H03G 11/00 (2006.01) H03K 5/08 (2006.01)

Patent

CA 1146626

1 PHB. 32,635. ABSTRACT: A voltage clamping circuit for use in coupling line voltage signals to logic control circuitry used in domestic appliances includes a voltage dropping resistor coupled between input and output terminals. A first enhancement mode MOS transistor is coupled between a junc- tion of the resistor and the output terminal and the VDD line. The gate of the first transistor is connected to the junction, so that when the voltage at the junction rises to a threshold voltage above VDD the first transis- tor is rendered conductive and clamps the positive line voltage cycle. A second enhancement mode MOS transistor is connected between the junction and the VDD line and its gate is connected to a biasing means which holds the second transistor nonconductive in response to the line voltage going negative until the junction is just above the VSS level, whereafter the second transistor turns on and clamps the input above VSS.

337416

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