Voltage random access memory (vram)

H - Electricity – 03 – M

Patent

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Details

H03M 1/78 (2006.01) H03M 7/00 (2006.01)

Patent

CA 2573147

An integrated circuit memory cell and voltage ladder design that adapts techniques typically applied to Static Random Access Memory (SRAM) circuits to implement a compact array of analog Voltage Random Access Memory (VRAM) locations. The memory cells in the VRAM each store a digital value that controls a corresponding switch. The switch couple a particular voltage from a set of voltages generated by the ladder, to be output when that location is enabled. Multiple analog output voltages are provided by simply providing additional rows of cells.

L'invention porte sur une conception de cellules de mémoire de circuits intégrés et de réseaux en échelles de tensions qui adaptent des techniques généralement appliquées à des circuits de mémoire vive statique pour mettre en place un réseau compact de points d'implantation de mémoires vives de tensions analogiques. Les cellules de la mémoire vive de tensions stockent chacune une valeur numérique qui commande un commutateur correspondant. Le commutateur est couplé à une tension particulière d'un ensemble de tensions générées par l'échelle, devant être générées lorsque le point d'implantation est validé. On obtient plusieurs tensions de sortie analogiques en ajoutant simplement des rangées de cellules.

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