Voting memory

Details Voting memory Voting memory

G - Physics

06

F

354/224

G06F 11/18 (2006.01)

Patent

CA 1175151

ABSTRACT OF THE DISCLOSURE A voting memory circuit for utilizing partially defective memory devices comprising first, second and third memory devices and at least one multiplexer circuit. Each memory device includes a plurality of address ter- minals for accessing a particular memory location in response to a multibit address signal and at least one data output terminal. Each address terminal of the first memory device is connected to one address terminal of each of the remaining memory devices. A first multiplexer circuit which includes at least three data input terminals, an output terminal and selector means for select- ing which data input terminal will be gated to the output terminal may be used to detect agreement of two out of three memory device outputs, Two of the memory device data output terminals are connected to the selector means and the remaining memory device data output terminal is connected to at least two of the multiplexer data input terminals. The multiplexer circuit provides an output signal which is that signal which occurs on at least two of the data output terminals of the memory devices Further, a second multiplexer circuit connected to the memory device data output terminals provides an indication when the memory device data output terminals are completely in agreement.

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