Watchdog timer

Details Watchdog timer Watchdog timer

G - Physics

06

F

324/59

G06F 11/00 (2006.01) G06F 1/24 (2006.01) G06F 9/48 (2006.01)

Patent

CA 1257908

ABSTRACT A self-checking timer (10) usable with a host system includes a clock and a plurality of interconnected counters (14), (24), (26), and (28). During a power-up phase, the timer generates a system reset signal and counts the counters in a predetermined sequence. A flip-flop (32) is set and reset during the power-up phase and inhibits generation of the system reset signal. During a normal operating phase, the timer (10) generates a test signal that must be responded to by the host system to continuously inhibit generation of the system reset signal.

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