Word line clamping circuit

Details Word line clamping circuit Word line clamping circuit

G - Physics

11

C

352/82.3

G11C 11/40 (2006.01) G11C 8/08 (2006.01) G11C 8/10 (2006.01)

Patent

CA 1097814

WORD LINE CLAMPING CIRCUIT Abstract of the Invention A word line clamping circuit for use with field effect tran- sistor memories is disclosed which permits the clamping of the word line to a reference potential using a minimum of devices and without the consumption of d.c. power so that multi-level bit line potentials may be utilized during the memory cycle. This is achieved by connecting a field effect transistor (FET) between word line and ground under control of a word line decoder so that a node associated with the last mentioned FET is held in either an uncharged or charged condition depending on whether the decoder is selecting its associated word line or not selecting it. Because the unselected word lines are held at ground during a portion of the memory cycle when reading or writing of memory cells associated with a selected word line is taking place, any capacitive coupling which might change the content of cells associated with unselected word lines is avoided and, for whatever the reason, bit line potentials may now be changed to different levels without affecting information storage during the memory cycle. Two circuits are shown which, under control of the word line decoder, permit the grounding of unselected word lines during at least a major portion of the memory cycle.

272841

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