Wordline voltage boosting circuits for complementary mosfet...

H - Electricity – 03 – K

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328/87

H03K 6/02 (2006.01) G11C 11/408 (2006.01) H03K 5/02 (2006.01) H03K 19/096 (2006.01)

Patent

CA 2000995

Two embodiments of a wordline boost clock circuit that can be used in high speed DRAM circuits are disclosed. The clock circuits require only one boost capacitor and discharge the wordlines faster, improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the nmos device which drives the load to negative during the boosting. In the first embodiment of the clock, the gate of a first device is connected to a first node through a second device. A second node, connected to a wordline, is discharged through the first and a third device when a third node is high with a fourth node low. After a sufficient discharge of the second node, the fourth node is pulled to VDD turning the second device on and a fourth device off. The first (NMOS) transistor has its gate and drain connected together and forms a diode. When a boost capacitor pulls the third node down to negative, the first device stays completely off because of its diode configuration and the second node is pulled to negative through the third device. In the second embodiment, a first device is connected between a boost capacitor and a second node. The load is discharged through a third device with a fourth device on but a first and second device off. After a sufficient dis- charge of the load, a fourth device is turned off but a second device is turned on, making the third device a diode. When a fifth node is pulled to ground, the second node is pulled down to negative with the first device on. In the second embodi- ment circuit, the load discharges through only one nmos device and consequently discharges faster than the circuit of the first embodiment.

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