Write error detecting hardware arrangement

Details Write error detecting hardware arrangement Write error detecting hardware arrangement

G - Physics

11

B

G11B 20/18 (2006.01) G06F 11/00 (2006.01) G06F 11/14 (2006.01)

Patent

CA 2069787

- 10 - NE-423 ABSTRACT OF THE DISCLOSURE An arrangement for detecting an error in writing data into a memory is disclosed. A data flow direction controller is responsive to a control signal applied thereto and allows data to be written, via a data terminal, into the memory during a preset time duration of a write cycle. The controller then steers the data, which corresponds to the data stored in the memory and which appears at the data terminal, to a data comparator in response to an error check timing signal which appears during a second preset time duration of the write cycle. The data comparator is therefore supplied with the original write data and the data already stored during the presence of the error check timing signal and produces a signal indicative of the error during the second preset time duration, in the event that the original write data does not coincide with the data indicative of what has been stored in response thereto.

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