Write-read/write-pass memory subsystem cycle

Details Write-read/write-pass memory subsystem cycle Write-read/write-pass memory subsystem cycle

G - Physics

06

F

354/233

G06F 12/08 (2006.01) G06F 13/16 (2006.01)

Patent

CA 1323446

ABSTRACT OF THE INVENTION Methods and apparatus for reducing memory read latency for selected data requested by one central processing unit (CPU) and retrieved from another CPU through a system control unit (SCU) with special data transfer cycles. The special data transfer cycles include a first dual operation mode which confirms that the transferred data is the most current and then concurrently writes the CPU transferred data into the SCU main memory while transferring it directly to the requesting CPU, and a second dual operation mode which confirms that only a portion of the transferred data is the most current and then concurrently writes the portion of the transferred data that is most current in the SCU memory and reads the written data that is most current in the SCU memory and reads the written data for transfer to the requesting CPU.

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