Write-shared cache circuit for multiprocessor system

Details Write-shared cache circuit for multiprocessor system Write-shared cache circuit for multiprocessor system

G - Physics

06

F

354/241

G06F 12/08 (2006.01)

Patent

CA 1306312

WRITE SHARED CACHE CIRCUIT FOR MULTIPROCESSOR SYSTEM Abstract of the Disclosure A "write-shared" cache circuit for multiprocessor systems maintains data consistency throughout the system and eliminates non-essential bus accesses by utilizing additional bus lines between caches of the system and by utilizing additional logic in order to enhance the inter- cache communication. Data is only written through to the system bus when the data is labeled "shared". A write- miss is read only once on the system bus in an "invalidate" cycle, and then it is written only to the requesting cache.

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