X-and-or memory array

Details X-and-or memory array X-and-or memory array

G - Physics

11

C

330/20, 352/82

G11C 17/00 (2006.01) G11C 7/06 (2006.01) G11C 7/14 (2006.01) G11C 7/18 (2006.01) G11C 11/40 (2006.01) G11C 17/12 (2006.01)

Patent

CA 1202724

-30- X AND-OR MEMORY ARRAY Abstract of the Disclosure A read-only memory array formed from a multi- plicity of NAND-organized FET stacks which are arranged in pairs and connected in alternate succession of adja- cent pairs at opposite ends. Selection of stacks by pairs is performed by connecting the common node of four stacks at one end to a bit line and the common node of another four stacks, only two being common with the former four stacks, to ground potential. Selection between adjacent stack pairs is performed by bank select FETs in each stack. Each stack is precharged at both ends prior to selection. A sense amp is utilized to compare the current sinking capacity of the selected bit line with a reference stack, the difference being de- tected in a differential amplifier. A programmable output driver provides an adjustable rate of change in the output signal for step input signals.

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