Zero-delay slew-rate controlled output buffer

H - Electricity – 03 – K

Patent

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Details

H03K 3/00 (2006.01) H03B 1/00 (2006.01) H03F 3/30 (2006.01) H03K 17/041 (2006.01) H03K 17/16 (2006.01) H03K 19/003 (2006.01) H03K 19/01 (2006.01) H03K 19/0175 (2006.01)

Patent

CA 2278475

An output buffer (100; 200) in accordance with the present invention exhibits a fixed output signal slew rate. The output signal behavior is independent of the capacitive load (CL) seen by the buffer. The circuit includes a capacitive feedback path from the output node to circuitry which drives the output transistors. In one embodiment, the feedback path comprises two capacitive elements (CFP, CFN), one which comes into play during a rising edge transition and the other which affects a falling edge transition. In a second embodiment, a single capacitive element (CF) is coupled to a switching circuit (P4, N4) for use during either a falling transition or a rising transition. The second embodiment provides precharging of the output transistor gates, and so improves response time.

Porte de puissance en sortie (100; 200) présentant une vitesse fixe de balayage du signal de sortie. Le comportement du signal de sortie est indépendant de la charge capacitive (CL) vue par la porte de puissance. Ce circuit comprend un trajet de rétroaction capacitif depuis le noeud de sortie jusqu'au circuit commandant les transistors de sortie. Dans un mode de réalisation, ce trajet de rétroaction est composé de deux éléments capacitifs (CFP, CFN), dont l'un joue un rôle pendant une transition de bord ascendante et l'autre pendant une transition de bord descendante. Dans un deuxième mode de réalisation, un seul élément capacitif (CF) est couplé à un circuit de commutation (P4, N4) afin d'être mis en application soit pendant une transition descendante, soit pendant une transition ascendante. Dans le deuxième mode de réalisation, les grilles du transistor de sortie sont préchargées, ce qui améliore le temps de réaction.

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