Zero power, electrically alterable, nonvolatile latch

Details Zero power, electrically alterable, nonvolatile latch Zero power, electrically alterable, nonvolatile latch

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G11C 16/04 (2006.01) G11C 11/40 (2006.01) G11C 14/00 (2006.01) H01L 27/10 (2006.01) H01L 29/788 (2006.01) H03K 3/356 (2006.01)

Patent

CA 1303689

-?- PATENT Abstract A compact, nonvolatile, zero static power, electrically alterable, bistable CMOS latch device is fabricated with single layer of polysilicon. The single polysilicon layer forms the floating gates of the nonvolatile elements of the device. The control gates are formed in the substrate by buried N+ diffusions and are separated from their respective floating gates by a thin oxide dielectric. The circuit can be designed to power-up in a preferred mode even before any programming operation has been performed on it. Thereafter, the circuit is available to be programmed to either of its two stable states. After the programming operation is completed and the circuit is latched to one of its two stable states, the fields across the thin oxide dielectrics are minimal and virtually no read disturb condition exist. Thus, the latch also offers excellent data retention characteristics.

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