Zero power high speed configuration memory

Details Zero power high speed configuration memory Zero power high speed configuration memory

G - Physics

11

C

G11C 8/00 (2006.01) G11C 7/10 (2006.01) G11C 8/18 (2006.01)

Patent

CA 2278615

A serial configuration memory device (100) comprises an architecture wherein the reading out of data and the outputting (52) of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme (34 and 44) is provided which allows the first byte to be pre- loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.

L'invention porte sur un dispositif (100) mémoire à configuration série qui présente une architecture dans laquelle la lecture des données et l'extraction (52) du train binaire se font en pipeline. En conséquence, le dispositif qui peut extraire un train binaire à partir uniquement de la fréquence d'une horloge externe n'est pas limité par la lenteur du circuit d'amplification de détection. Un dispositif (34 et 44) d'antémémoire permet de précharger le premier octet au cours d'un cycle d'initialisation de sorte que le dispositif peut commencer aussitôt à extraire le train binaire à l'achèvement du cycle. Selon une réalisation préférée de l'invention, le train binaire comprend des emplacements mémoire accessibles en série à partir de l'emplacement mémoire zéro. Selon une autre réalisation, le train binaire peut commencer à partir d'un emplacement mémoire autre que zéro.

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