Method for the manufacture of a monolithic static memory cell

Details Method for the manufacture of a monolithic static memory cell Method for the manufacture of a monolithic static memory cell

H - Electricity

01

L

356/197, 352/34

H01L 27/11 (2006.01) G11C 11/35 (2006.01)

Patent

CA 1145041

ABSTRACT OF THE DISCLOSURE A high bit density is provided for static memory cells in which a semiconductor layer carried on a semiconductor body has strip-shaped insulation zones extending to the semiconductor body and limiting a memory cell. A gate oxide layer is applied to the boundary surface of the semiconductor layer and has a polysilicon layer which is highly doped and covered with a first inter- mediate oxide layer. A drive line and the gate are structured by a first, selective, vertically aligned, reactive plasma etching process. Sections of the drive line at the ends thereof are removed by isotropic etching and the resulting recesses are filled in a thermal oxidation step. The portion of the gate oxide layer adjacent the structured parts is removed by a second, select- ive, vertically aligned, reactive plasma etching process. A second poly- silicon layer is deposited, highly doped and covered with a second intermediate oxide layer. Another drive line having a part contacting a doped region in the semiconductor layer, the region being formed by ion implantation, is structured by a third, selective, vertically aligned, reactive plasma etching process. A recess is then formed by a fourth, selective, vertically aligned, reactive plasma etching process and an isotropic etching step is performed to remove those parts of the drive line which extend to the last-mentioned recess. A fifth, selective, vertically aligned, reactive plasma etching process is per- formed for removing the oxide layer covering the boundary surface of the semi- conductor layer within the recess. A third, silicon layer is deposited and covered with a third intermediate oxide layer. Another recess is formed in the third intermediate oxide layer above the recess provided by the fourth reactive plasma etching process in a sixth, selective, reactive plasma etching process. A conductive coating is then applied to the third polysilicon layer and is provided with an electrical terminal.

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