Semiconductor wafer dicing fixture

H - Electricity – 01 – L

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356/191

H01L 21/68 (2006.01) B25B 11/00 (2006.01) B28D 5/00 (2006.01) H01L 21/683 (2006.01)

Patent

CA 1053383

SEMICONDUCTOR WAFER DICING FIXTURE Abstract of the Disclosure This patent discloses apparatus for retaining a semiconductor wafer in a predetermined position or orientation to permit dicing of the wafer into discrete semiconductor chips of a predetermined size without dislocation of the chips during the dicing operation, the chips being arranged in columns and rows with a kerf area intermediate adjacent chips. The apparatus comprises a base member having a semiconductor wafer positioning area with a connection to the base member for applying the vacuum to a plurality of spaced apart apertures in the wafer receiving area, the apertures corresponding to the location of the chips. A cover plate, adapted for superimposition of the wafer receiving area, includes a plurality of interdigitated ribs and slots, the slots extending through the cover and dimensioned for alignment with the kerf area of the wafer, the ribs having strips of compressible material underlying the ribs for superimposed pressing relation on the wafer so that when a wafer is being cut through the slots along the kerf area, the vacuum being drawn coupled with the pressing engagement of the strips on the wafer inhibit dislocation of the chips during the dicing operation. The purpose of this abstract is to enable the public and the Patent Office to determine rapidly the subject matter of the technical disclosure of the Application.

266529

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