H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/147, 352/82.
H01L 27/08 (2006.01) H01L 21/8236 (2006.01) H01L 21/8246 (2006.01)
Patent
CA 1111147
ABSTRACT OF THE DISCLOSURE A method is disclosed for selectively modifying the electrical characteristics of MOS devices at a late stage in the fabrication process to form, for example, the "I" and "O" data locations of a ROM, or to form enhancement-and depletion-mode devices. In one embodiment of the method, in addition to forming openings in the passivation layer to define location of bonding pads, additional openings are formed in that layer at locations at which a data bit of one of the two levels is to be formed. Subsequently, an ion implantation is performed through the exposed underlying polysilicon gate structure to create an implantation layer at the channel regions of se- lected MOS devices, and thereby permanently alter the threshold voltages of these MOS devices. Other embodiments of the invention are disclosed in which ion implantation is performed through openings selectively formed in other layers, thereby to form implantation regions at selected locations to modify selected MOS devices at those locations.
288419
Smart & Biggar
Smc Standard Microsystems Corporation
LandOfFree
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