Floating point addition architecture

Details Floating point addition architecture Floating point addition architecture

G - Physics

06

F

354/204

G06F 7/50 (2006.01) G06F 5/01 (2006.01)

Patent

CA 1184664

FLOATING POINT ADDITION ARCHITECTURE Abstract Parallel shifter architecture in an arithmetic unit of a digital computer for processing floating point mantissas. An arithmetic-logic unit (ALU) in series with shifting means functions in parallel with a barrel shifter, Both paths are executed simultaneously and the output of one path is selected for storage at the end of a microcycle based on machine status and the actual floating point numbers manipulated. This architecture provides a significant reduction in floating point addition execution time.

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