High speed adder

G - Physics – 06 – F

Patent

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354/197

G06F 7/50 (2006.01)

Patent

CA 1294367

HIGH SPEED ADDER ABSTRACT An improved cascadable adder (11) is disclosed which, through the use of merged logic, provides high speed operation in the presence of input loading and internal fan-out limitations. The invention may be implemented in gallium arsenide technology and includes a first circuit (13) for exclusive ORing first bits (A1, B1) of first and second digital words (A1, B1) respectively; and a second circuit (37) operatively connected to the first circuit (13) for generating, with only two gate delays, a carry (C1) associated with the summing of the first bits.

577047

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