Silicon gigabit metal-oxide-semiconductor device processing

Details Silicon gigabit metal-oxide-semiconductor device processing Silicon gigabit metal-oxide-semiconductor device processing

H - Electricity

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356/149

H01L 21/28 (2006.01) H01L 21/31 (2006.01) H01L 21/321 (2006.01) H01L 21/336 (2006.01) H01L 29/08 (2006.01)

Patent

CA 1216374

- 10 - SILICON GIGABIT METAL-OXIDE-SEMICONDUCTOR DEVICE PROCESSING Abstract In a metal-oxide-semiconductor device process, parasitic capacitance is significantly reduced by producing a spacer of insulating material (e.g., 41, 42) on a gate mesa (e.g., 22) and exposed portions of a substrate (e.g., 14 and 15), by differentially oxidizing a substrate and a gate mesa thereon prior to ion implantation and "drive-in" of the drain and source regions (e.g., 13 and 11, respectively, and 12). This results in a channel region being formed in the substrate beneath and substantially coextensive with the gate mesa. The conductivity of the channel region is different from the conductivity of the adjacent source and drain regions. In one embodiment, the source and drain regions each extend to a greater depth into the substrate with increasing distance from the channel region. (FIG 3)

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