Maximum length pseudo-random test pattern generator via...

Details Maximum length pseudo-random test pattern generator via... Maximum length pseudo-random test pattern generator via...

G - Physics

06

F

356/117

G06F 11/26 (2006.01) G01R 31/28 (2006.01) G01R 31/3181 (2006.01) G06F 7/58 (2006.01)

Patent

CA 1298668

Abstract A system and method for generating 2n test patterns is disclosed. The system utilizes a linear feedback shift register (LFSR) to generate a sequence of 2n-1 test patterns. In addition, the system includes apparatus external to the shift register which generates a 2nth test pattern. A switching circuit is employed to insert the 2nth test pattern into the sequence of test patterns. Therefore, a 2n test pattern sequence is generated. The test pattern sequence produced is pseudo-random in nature. The system further includes an output for providing a test pattern; such output could be used for the testing of a VLSI sub-system such as ROM. A method utilizing the techniques embodied in the system is also disclosed.

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