Prefetching mechanism for a high speed buffer store

Details Prefetching mechanism for a high speed buffer store Prefetching mechanism for a high speed buffer store

G - Physics

06

F

354/230.87

G06F 12/08 (2006.01) G06F 9/38 (2006.01)

Patent

CA 1217870

A B S T R A C T PREFETCHING MECHANISM FOR A HIGH SPEED BUFFER STORE An efficient prefetching mechanism is disclosed for a system comprising a cache. In addition to the normal cache directory, a two-level shadow directory is provid- ed. When an information block is accessed, a parent identifer derived from the block address is stored in the top level of the shadow directory. The address of a subsequently accessed block is stored in the second level of the shadow directory, in a position associated with the first-level position of the respective parent identi- fier. With each access to an information block, a check is made whether the respective parent identifier is already stored in the first level of the shadow directory. If it is found, then the descendant address from the associated second-level position is used to prefetch an information block to the cache if it is not already resident therein. This mechanism avoids with a high probability the occur- ence of cache misses.

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