Buffer system with detection of read or write circuits failures

Details Buffer system with detection of read or write circuits failures Buffer system with detection of read or write circuits failures

G - Physics

06

F

354/224

G06F 11/10 (2006.01) G06F 5/10 (2006.01) G06F 7/78 (2006.01)

Patent

CA 1222058

BUFFER SYSTEM WITH DETECTION OF READ OR WRITE CIRCUITS FAILURES ABSTRACT An improved data buffer has a storage array that is addressable for read and write operations by an address of n bits that are supplied by a read address counter and a write address counter that each have n + 1 bits. The n + 1th bit is in effect a counter for passes through the array by the read and write circuits. During a write operation the n + 1th bit of the write counter is stored as part of a parity bit for the addressed array location. During a read operation the n + 1th bit of the read address counter is entered into a parity checking function on the word read from the addressed location. An error is signaled if the n + 1th bit of the read address counter does not agree with the n + 1th bit of the write counter at the time of the write operation. For example, an error is detected if the write circuits fail and the read circuits make a second pass through words that have previously been read, the same entries on a next pass through the array.

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