Method and apparatus for a parallel carry generation adder

Details Method and apparatus for a parallel carry generation adder Method and apparatus for a parallel carry generation adder

G - Physics

06

F

354/204

G06F 7/50 (2006.01)

Patent

CA 1323106

ABSTRACT OF THE INVENTION The parallel carry generator of the present invention calculates the carry for a m bit number within log2n + 1 gate delays where n is smallest binary ordered number greater than or equal to m. Thus in the parallel carry generation adder of the present invention, the sum is calculated in log2n + 2 gate delays. Thus, a 32 bit carry computation can be performed in as little as 6 gate delays. This is achieved by breaking down the 32 bit word according to binary ordered values and cascading portions of the calculations required wherein the carry generated for the most significant bit of the lower binary ordered group is used to calculate the carrys for the bits in next higher ordered group By ordering the bits and the logic circuitry in this manner, the amount of gate delays to perform the carry calculation is minimized without excessively increasing the amount of logic.

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