Memory readback check apparatus

Details Memory readback check apparatus Memory readback check apparatus

G - Physics

06

F

354/224

G06F 11/32 (2006.01) G06F 11/10 (2006.01) G06F 12/16 (2006.01) G11C 29/00 (2006.01) G06F 11/00 (2006.01)

Patent

CA 1310761

ABSTRACT Disclosed is a memory check apparatus capable of detecting any position difference of output data due to erroneous data written into a memory. The memory check apparatus comprises a memory check circuit for a memory system using a plurality of memories whose write addresses and read addresses are updated in response to a data write clock pulse, and a data read clock pulse, respectively. A selector inserts unique word for data error detection into input data at predetermined intervals. A write clock pulse generator supplies the write clock pulse to each of the plural memories, while a read clock pulse generator supplies the read clock pulse to each of the plural memories. A unique word detector detects the unique word from data read out of the plural memories in response to the read clock pulse and generates a detection signal. A reset circuit generates a reset signal to reset the plural memories if said detection signal is not generated within a predetermined period of time.

575174

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