Memory cell power scavenging apparatus and method

Details Memory cell power scavenging apparatus and method Memory cell power scavenging apparatus and method

G - Physics

11

C

354/221

G11C 13/00 (2006.01) G11C 5/14 (2006.01) G11C 8/08 (2006.01) G11C 11/414 (2006.01)

Patent

CA 1238419

MEMORY CELL POWER SCAVENGING APPARATUS AND METHOD ABSTRACT OF THE DISCLOSURE The present invention Utilize the power available for application to a static RAM cell 1 in inner which provides efficient use of the power to that greater standby power by be applied to the static RAM to increase the memory speed. the current required to maintain the memory cell i in a speed. state flows from the Ucc source through o row of parallel memory cells and through a common bits supply and and various peripheral circuits, such as decoders. A shunt voltage regulator controls the dependence of the common bias supply voltage on current fluctuations caused by addressing and deaddressing the memory cells. The invention includes an isolation device for isolating a particular row of memory cells when it is addressed without disturbing the bias on other memory cell rows. Similarly, the reference voltages of each of the peripheral circuits can be made independent of the common bias supply voltage and independent of the other peripheral circuits by the use of a local voltage regulator on each peripheral.

494919

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