Bay packing method and integrated circuit employing same

Details Bay packing method and integrated circuit employing same Bay packing method and integrated circuit employing same

H - Electricity

01

L

356/133

H01L 27/00 (2006.01) G06F 17/50 (2006.01) H01L 23/52 (2006.01)

Patent

CA 1199428

BAY PACKING METHOD AND INTEGRATED CIRCUIT EMPLOYING SAME ABSTRACT OF THE DISCLOSURE A wire packing method for packing wire segments in wiring bays of large-scale integrated circuit devices and integrated circuit devices produced employing such a method. Each wiring segment to be placed in a channel of a wiring bay is assigned a score in accordance with criteria developed for the particular application. The start point, end point and a segment identifier is recorded for each segment to be packed. For each channel, segments which can be considered candidates for packing in that channel are extracted from the list. For that channel, moving forwardly from one end of the channel, at the end point of each segment, a total score is calculated by adding to the score of that segment a best score occurring before the start point of the segment. If the total score exceeds a present value of a best string score for nonoverlapping segments, the present value of the best string score is replaced by the new total score, otherwise the present value of the best string score is retained. When the other end of the bay is reached, moving back towards the first end, segments are assigned to the channel for which the total score therefor exceeded the then-present value of the best string score and which do not overlap already-assigned segments.

453486

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