Frame detection and synchronization system for high speed...

H - Electricity – 04 – L

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340/74

H04L 1/00 (2006.01) H04J 3/06 (2006.01)

Patent

CA 1178680

D-23,646 FRAME DETECTION AND SYNCHRONIZATION SYSTEM FOR HIGH SPEED DIGITAL TRANSMISSION SYSTEMS By Robert A. Karchevski ABSTRACT OF THE DISCLOSURE A framing detector and frame synchronization arrangement for a framing pattern, other than a winking framing pattern consisting of alternating 1's and 0's, in a high speed digital system comprises a preview store having a plurality of stages, each capable of storing a like number of bits, and timing means synchronized with incoming binary data for clocking the like number of bits into each stage of the preview store on the occurrence of each framing bit. A comparator compares the state of the present incoming data bit with stored outputs from selected stages of the preview store to determine if these bits constitute a valid framing sequence, and provides a binary output of one state for a valid sequence and of the other state otherwise. An error density detector is included for providing an error signal indication when a predetermined error rate is exceeded and counting means is responsive to the output signals from the error density detector and the comparator for either permitting the clocking in of the like number of bits when the comparator output indicates that a valid framing sequence exists at a frame interval, or permitting a bit by bit comparison as the bits stored in the preview store are stepped one bit at a time for valid framing sequence comparison, the stepping sequence being stopped by the occurrence of a valid frame sequence as determined by the output of the comparator, or by stepping through the like number of bits, whichever occurs first; should the latter occur, the timing means reading into the preview store a like number of bits for comparison with the bit at the next frame bit location.

398567

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