Interface processor unit

Details Interface processor unit Interface processor unit

G - Physics

06

F

354/224, 354/233

G06F 11/28 (2006.01) G06F 13/28 (2006.01) G06F 15/163 (2006.01) G06F 15/17 (2006.01)

Patent

CA 1180820

INTERFACE PROCESSOR UNIT Abstract A data communication arrangement in which an interface processor effects the transmission of messages between two processors of a multiprocessor system. The interface processor is connected to the communicating procesors via direct memory access circuits. A processor stores messages in a send buffer in memory and controls a pointer in memory indicating the loading of such a buffer. The interface processor reads this pointer and the messages, and writes a pointer and the messages in a receive buffer of a receiving processor. The interface processor limits the loading of new messages into the send buffer by delaying the updating of an unload pointer, creating memory space for new messages, until the receiving processor has processed the transmitted messages. Messages can also be used to initiate the transfer of a block of data from the memory of one processor to that of another. Initialization of the interface processor is a joint effort of the communicating processors.

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