Double-buffered time division switching system

Details Double-buffered time division switching system Double-buffered time division switching system

H - Electricity

04

Q

363/17

H04Q 11/04 (2006.01) H04Q 11/08 (2006.01)

Patent

CA 1292334

Abstract of the Disclosure There is described an improved double-buffered time division switching system comprising first and second k- bit x N-multiplex memory switches, into whose N time slots per frame are sequantially inputted time division multiplexed data and either of which is placed in a write state. A control memory is provided for storing the read sequence of data in the first and second memory switches. First and second multi-element information memories store multi-element information which indicates, corresponding to a plurality of input time slots constituting a series of data in the frame, that these time slots are multi- element data. A first controller checks the first multi- element information memory in synchronism with the writing of input time slots into the memory switches and, if the multi-element information is stored corresponding to the time slots into which to write, alternately switches the data writing of the time slots between the first and second memory switches on a frame-by-frame basis. A second controller checks the second multi-element information memory in synchronism with the reading into output time slots from the memory switches and, if the multi-element information is stored corresponding to the time slots to output, outputs into the output time slots alternately data read out of the first memory switch and one read out from the second memory switch on a frame-by- frame basis.

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