Cache-memory architecture

Details Cache-memory architecture Cache-memory architecture

G - Physics

06

F

354/241

G06F 13/20 (2006.01)

Patent

CA 1323451

ABSTRACT A cache-memory system comprising a processor bus communicating with an associated processor (CPU) in said system; a plurality of cache-memory management units (CMMUs) on said processor bus each having a single cache address tag array for addressing one associated cache array, and each one of said plurality of CMMUs communciating through an associated one of a plurality of memory buses with a main memory of said system.

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