Microprocessor with improved instruction cycle

Details Microprocessor with improved instruction cycle Microprocessor with improved instruction cycle

G - Physics

06

F

354/230.87

G06F 13/14 (2006.01) G06F 9/32 (2006.01) G06F 9/38 (2006.01)

Patent

CA 1242802

ABSTRACT OF THE DISCLOSURE A microcomputer includes an instruction decoder and a program counter. The instruction decoder decodes fetched instructions and outputs a control signal ordering execution of the fetched instruction. The control signal from the instruction decoder includes a component controlling fetch cycles which triggers a fetch cycle at the beginning of each instruction cycle to fetch the operand for the instruction currently being executed and midway through each instruction cycle to fetch the OP code for the next instruction. The program counter is responsive to the triggering of each fetch cycle to increment its counter value so as to keep the counter value consistent with the address being accessed in each fetch cycle.

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