Processor access control arrangement in a multiprocessor system

Details Processor access control arrangement in a multiprocessor system Processor access control arrangement in a multiprocessor system

G - Physics

06

F

354/233

G06F 13/36 (2006.01) G06F 9/46 (2006.01) G06F 15/16 (2006.01)

Patent

CA 1278387

PROCESSOR ACCESS CONTROL ARRANGEMENT IN A MULTIPROCESSOR SYSTEM Abstract In a multiprocessor system, processors are connected to an interconnecting bus by means of bus interface circuits which comprise an address buffer in addition to data buffers. The interconnecting bus, in addition to a destination address and data also carries an originating address identifying the processor transmitting the data. In the event of a receive buffer overload condition in the receiving bus interface circuit, a negative acknowledge signal is transmitted on the bus and the originating address is queued in the address buffer. When the buffer overflow condition has been relieved, a retransmission request is sent to the first processor identified in the address buffer and its message is received. This procedure will be repeated for each processor identified in the address buffer.

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