H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/149, 356/172
H01L 21/18 (2006.01)
Patent
CA 1199429
VERTICAL CHANNEL FIELD CONTROLLED DEVICE EMPLOYING A RECESSED GATE STRUCTURE AND METHODS OF MAKING ABSTRACT OR THE DISCLOSURE A vertical channel junction gate electric field con- trolled device (e.g., a field effect transistor or a field con- trolled thyristor) includes a semiconductor base region layer, and a plurality of grooves having vertical walls formed in the upper surface of the base region layer. Between the grooves on the upper surface of the base region layer but not extending to the grooves are upper electrode regions, for example, source electrode regions or cathode electrode regions. Formed in the groove bottoms and sidewalls are junction gate regions. Upper electrode terminal metallization is evaporated generally on the upper device layer, and gate terminal metallization is over the junction gate regions at the bottoms of the grooves. The disclosed structure thus has continuous metallization along the recessed gate regions for a low-resistance gate connection. The structure facilitates fabrica- tion by methods, also diclosed, which avoid any critical photo- lithographic alignment steps in masking to define the locations of the source (or cathode) and gate regions, and avoid the need for any mask or mask alignment for metal definition when forming elec- trode metallization. As a result of the structure of the upper electrode and gate regions, it is not critical to avoid any metal deposition on the groove sidewalls.
417900
Baliga Bantval J.
Love Robert P.
Company General Electric
Eckersley Raymond A.
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