Frame arrangement for multiplexing a plurality of...

H - Electricity – 04 – J

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H04J 3/16 (2006.01) H04J 3/00 (2006.01) H04J 3/12 (2006.01)

Patent

CA 1229184

Abstract of the Disclosure In order to multiplex a plurality of various rate subchannels onto a fixed rate channel, a frame structure is defined consisting of sets of i-tuples for a total of ij bits per frame, the parameters i and j being mathematically determined as a function of the rate of the subchannels and the rate of the fixed channel. For j-l of the i-tuples, i-l bits are used for information and the last bit is set ONE. In one i-tuple all i bits are set ZERO. Framing is detected by monitoring for a ONE followed by i ZEROes, a pattern which cannot occur elsewhere in the frame regardless of the data. An integral number of information bits from each subchannel are distributed in the (i-l)(j-l) information bit positions. In the disclosed embodiment two 666-2/3 bps channels and a 4800 bps channel are multiplexed onto an 8000 bps channel using a frame structure consisting of 24 quintets. In the 92 information bit positions, 72 bits are allocated for the 4800 bps channel and 10 bits each are allocated for the 666-2/3 bps channels. The multiplexer shifts the input bits through shift registers (403, 404, 406) and selects (407) for output at the 8000 bps rate one of the stored input bits or a set ONE or ZERO as determined by a sequencer 410. The demultiplexer shifts the bits in the multiplexed bit streams through a shift register (802) and selects (814) as determined by a sequencer 813 appropriate stored bits for output in the demultiplexed bit streams. Framing is maintained by a pattern detector (804) which is responsive to only a ONE followed by five ZEROes in the multiplexed stream.

486760

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