Bidirection buffer with latch and parity capability

Details Bidirection buffer with latch and parity capability Bidirection buffer with latch and parity capability

H - Electricity

04

L

340/75

H04L 5/14 (2006.01) G06F 11/10 (2006.01) G06F 13/40 (2006.01) H03K 19/082 (2006.01)

Patent

CA 1338155

A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

596778

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