Method and means for instruction combination for code...

Details Method and means for instruction combination for code... Method and means for instruction combination for code...

G - Physics

06

F

354/230.7

G06F 9/30 (2006.01) G06F 9/315 (2006.01) G06F 9/38 (2006.01)

Patent

CA 1254661

ABSTRACT In a computer device having a reduced instruction set architecture, frequently occurring operations are combined into a single instruction in accordance with the invention, and the single instruction executes the combined operations simulta- neously. Specifically, the frequently used instructions for moving data and then branching are combined into a single instruction in a computer device in accordance with the preferred embodiment of the invention for concurrent execution. As a result, both code compaction and higher execution speed are achieved with the invention.

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