Pause apparatus for a memory controller with interleaved...

Details Pause apparatus for a memory controller with interleaved... Pause apparatus for a memory controller with interleaved...

G - Physics

06

F

354/234

G06F 9/46 (2006.01) G06F 13/18 (2006.01) G06F 13/28 (2006.01)

Patent

CA 1182578

ABSTRACT OF THE DISCLOSURE A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller which controls the operation of a number of memory module units and includes a number of queue circuits for storing memory requests to be processed. The memory controller further includes control apparatus connected to monitor bus activity. In response to certain bus activity conditions occurring during multiword transfer operations, the control apparatus operates to lengthen the time between successive multiword transfers of data to the bus so as to ensure that new requestors having lower priorities than a memory controller gain access to an available queue notwithstand- ing the amount of bus delay incurred in transmitting their memory requests.

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