Binary logic structure employing programmable logic arrays...

Details Binary logic structure employing programmable logic arrays... Binary logic structure employing programmable logic arrays...

G - Physics

06

F

354/230.71

G06F 9/40 (2006.01) H03K 19/177 (2006.01)

Patent

CA 1187189

ABSTRACT BINARY LOGIC STRUCTURE EMPLOYING PROGRAMMABLE LOGIC ARRAYS AND USEFUL IN MICROWORD GENERATION APPARATUS Binary logic structure is described which requires less space on an integrated circuit chip. This structure includes an encode programmable logic array responsive to a first group of binary input signals for producing a smaller number of binary signals which are encoded to identify different binary value combinations for the first group of binary input signals. This structure further includes a decode programmable logic array responsive to a second group of binary input signals and to the encoded binary signals produced by the encode programmable logic array for producing binary output signals representing logical functions of binary input signals in both the first and second groups. The chip space occuppied by the encode pro- grammable logic array is less than the additional chip space that would be required if the encode and decode programmable logic arrays were replaced by a single programmable logic array for receiving all the binary input signals in both the first and second groups. When used to provide microword generation apparatus for a microprogrammed digital system, the encode program- mable logic array is responsive to a plural-bit system instruction for producing a plural-bit instruction identification signal uniquely representative of such system instruction but having a smaller number of bits than the system instruction. In such case, the decode programmable logic array is responsive to the instruc- tion identification signal and to number signals pro- duced by a sequence counter for producing a sequence of microwords needed to execute the system instruction.

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